This invention relates generally to integrated circuits for performing digital multiplication, and, more particularly, to multiplier circuits that are also capable of performing product accumulation. Integrated or monolithic circuits for performing digital multiplication are, of course, well known. Briefly, and by way of background, such multipliers operate on a digital, and usually binary, multiplier quantity, and a corresponding digital multiplicand quantity, to generate a binary product. Typically, the multiplier and multiplicand have equal numbers of binary digits. If the full significance of the quantities multiplied together is to be retained, the product will contain twice as many binary digits (bits) as either the multiplier or the multiplicand. Such digital multipliers may usually be operated in one of two modes; an integer mode, in which the quantities being multipled are treated as positive integers, and a two's complement mode, in which the multiplier, multiplicand, and product are each represented as signed, i.e. positive or negative, binary fractions.
In some applications of multipliers, it is necessary to accumulate or add together a sequence of products derived from a succession of pairs of numerical quantities. Although this accumulation function may be performed by logic external to the multiplier circuit, it is clearly more efficient to provide an accumulation function in the same integrated circuit as the multiplier. One example of a multiplier-accumulator for multiplying pairs of twelve-bit quantities and accumulating the resulting products, is the Model TDC1003J, manufactured by TRW LSI Products, Redondo Beach, Calif. 90278. When the accumulation function is rendered operable in this circuit, each product quantity is added to the contents of an accumulator register, or, at the user's option, the contents of the accumulator register are subtracted from the product and stored back in the accumulator register.
Although multiplier-accumulators of this general type are perfectly satisfactory for many applications, there are some computations in which it is desirable to be able to preload the accumulator register with a selected value, and then to begin further accumulation of products in the register. The value to be preloaded into the accumulator register might, for example, represent an interim accumulation of products which was temporarily stored externally, while the multiplier-accumulator was being used for other computations. Again, logic for performing the equivalent of such a preloading function could be provided externally to the multiplier-accumulator circuit. For example, an initial quantity P could be stored in the accumulator register by multiplying P by 1.0 and conditioning the circuit for pure multiplication, i.e. no accumulator function. However, such external logic is inherently inefficient because of the additional time delay that it introduces in performing the required arithmetic functions.
It will be appreciated from the foregoing that there is a significant need for an integrated circuit which will perform the aforedescribed functions, and will thereby effect a considerable reduction in complexity and computation time in contrast to comparable techniques utilizing external logic. Ideally, any circuit for presetting the contents of the accumulator register in a multiplier-accumulator should be operable to preset only selected fields of the register, and to leave the unselected fields intact. The present invention is directed to these ends.